1. Field of the Invention
The present invention relates to a memory device and also to a data processing device, each having a RAM whose state is transferred from active to non-active in response to a change in voltage of a power source. In particular, the present invention pertains to an improper writing prevention circuit which prohibits false or improper writing to a RAM due to malfunction of a MPU (microprocessor unit) which may occur as a result of an unstable voltage condition of the power source.
2. Prior Art
RAMs have been widely used as semiconductor memory for word processors, personal computers, home computer game machines etc., one known type being the SRAM (Static RAM). The typical RAM, which is known as a back-up type RAM, is provided with an auxiliary power unit which has a secondary battery to retain memory contents in the RAM after the main power is shut off.
FIG. 3 is a block diagram which shows a conventional semiconductor memory device 10 having a back-up type RAM (12). The semiconductor memory device 10 shown in this figure is comprised of a typical back-up type RAM 12, a source-voltage detection circuit 14 and a power source changeover switch 16. The back-up type RAM 12 has address terminals A0-A7 for receiving address signals via an address bus from a control block 20 having a microprocessor unit 22. The RAM 12 also has input-output terminals D0-D7 (data terminals) for input of data transferred via a data bus from the control block 20 during a writing operation mode and for output of data via the data bus to the control block 20 during a reading operation mode, a first chip-enable or chip selection terminal CEI of the MPU 20 for determining the state of the memory chip (RAM) 12, a read-write terminal R1 for receiving instructions of data reading and writing, a power terminal (high voltage side terminal) V.sub.DD connected to a power source whose voltage is usually 5V, a ground terminal V.sub.ss connected to a point at ground voltage (low voltage), and a second chip-enable terminal CE2 for determining the state of the RAM, i.e. an active state ready for writing and/or reading, or in static state (non active state) for holding stored data therein.
The source voltage detection circuit 14 functions such that it compares source voltage V.sub.DD with a threshold voltage V.sub.th (approx. 3.3V-4.5V), and, in response to a drop by a value V.sub.x of the source voltage V.sub.DD lower than the threshold voltage Vth due to the cutoff of the source voltage V.sub.DD, generates a power source changeover signal S1 to thereby determine the starting point at which the power source is changed to the back-up power supply. The power source changeover switch 16 connects the power (high voltage) terminal V.sub.DD of RAM 12 selectively to the source voltage V.sub.DD or the secondary battery B (approx. 3V) for back-up operation in accordance with the power source changeover signal S.sub.1.
For example, if the source voltage supply is cut off by opening a power switch SW, the source voltage detection circuit 14 detects a drop of the voltage value supplied thereto and generates the power source changeover signal S.sub.1. In response to this signal, the power source changeover switch 16 is shifted from the power terminal V.sub.DD to the side of the back-up secondary battery B. At the same time, the state of the RAM is transferred to the static state in which the data are maintained as they are in a reduced power-consumption mode. During the static state of the RAM, the power source changeover signal S.sub.1 maintains a high level signal at second chip-enable terminal CE2, so that data writing or reading are prevented.
The back-up type RAM 12 is changed to the static state not only when the power supply is switched from the main power source to the auxiliary power source due to the shutoff of the main power, but also during a transient change in the source vol&age immediately after the main power is placed into service by closing the power switch SW. The change in the state of the RAM 12 to the static state also occurs in the event of an unstable condition of the power source which may be caused, for example, by instantanecus or short black out, during the normal operation period.
Usually, a writing operation to the RAM 12 is performed under the control of the microprocessor 22 wherein the threshold voltage V.sub.th the source voltage detection circuit 14 must be exactly the same as a guaranteed lowest voltage V.sub.min for operation of the microprocessor 22. However, it is extremely difficult to manufacture a microprocessor so that it has exactly the same value of threshold voltage V.sub.th as that of the guaranteed lowest voltage V.sub.min for operation mainly because all semiconductor chips (microprocessors) cannot be manufactured to exhibit exactly the same voltage V.sub.min. Also, although the source voltage detection circuit 14 is required to detect the voltage V.sub.x accurately, the detected value usually involves a relatively large error component.
The above problems can give rise to a number of drawbacks. For example, under the condition that the threshold voltage V.sub.th is higher than the guaranteed voltage for operation V.sub.min that the voltage detection value V.sub.x is in the range between the threshold voltage Vth and the guaranteed lowest voltage for operation V.sub.min, even where the microprocessor 22 is ready for normal service, writing into the RAM 12 is impossible since the state of the RAM 12 will have been transferred to the static state. On the other hand, under the condition that the threshold voltage V.sub.th is lower than the guaranteed lowest voltage for operation V.sub.min and that the detected voltage V.sub.x is in the range of the value between the guaranteed lowest voltage for operation V.sub.min and the threshold voltage Vth , although the microprocessor 22 is out of the guaranteed operational condition, RAM 12 is in an active sate so that false data can be undesirably accepted by the RAM 12 when a malfunction occurs in the microprocessor 22.
Thus, in case the detected voltage of the source voltage detection circuit 14 of the RAM 12 is lower than the guaranteed lowest voltage for operation V.sub.min of the microprocessor 22, and RAM 12 remains in its active state, the probability of malfunction of the microprocessor 22 is very high, and therefore, if a writing malfunction occurs, RAM 12 is allowed to be written improperly. The improper writing can destroy stored data and cause a decrease in the reliability of the data processing unit.
In case the detected voltage is far below the guaranteed lowest voltage for operation V.sub.min to the extent that it reaches a value where action stops, obviously, the microprocessor 22 cannot be driven into service. When the detected voltage is in the range between the guaranteed lowest voltage for operation V.sub.min and the above value where action stops, the probability of malfunction goes to a high level from a low level. The above-mentioned probability density becomes higher as the difference between the lowest value V.sub.min and the value action stops becomes smaller, whereas this density becomes lower as the aforesaid difference becomes larger. Thus writing malfunctions occur in accordance with the probability of malfunction of the microprocessor.